65. Unsigned DIVide

65.1. Name

DIVU, DIVUL -- Unsigned divide

65.2. Synopsis

        DIVU.W        <ea>,Dn     32/16 -> 16r:16q
        DIVU.L        <ea>,Dq     32/32 -> 32q      (68020+)
        DIVU.L        <ea>,Dr:Dq  64/32 -> 32r:32q  (68020+)
        DIVUL.L       <ea>,Dr:Dq  32/32 -> 32r:32q  (68020+)

        Size = (Word, Long)

65.3. Function

Divides the unsigned destination operand by the unsigned source operand and stores the unsigned result in the destination. The instruction has a word form and three long forms.

For the word form, the destination operand is a long word and the source operand is a word. The resultant quotient is placed in the lower word of the destination and the resultant remainder is placed in the upper word of the destination. The sign of the remainder is the same as the sign of the dividend.

In the first long form, the destination and the source are both long words. The quotient is placed in the longword of the destination and the remainder is discarded.

The second long form has the destination as a quadword (eight bytes), specified by any two data registers, and the source is a long word. The resultant remainder and quotient are both long words and are placed in the destination registers.

The final long form has both the source and the destination as long words and the resultant quotient and remainder as long words.

65.4. Format

        In the case of DIVU.W:
        ~~~~~~~~~~~~~~~~~~~~~                              <ea>
        ----------------------------------------=========================
        |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|-----------|---|---|---|-----------|-----------|
        | 1 | 0 | 0 | 0 | REGISTER  | 0 | 1 | 1 |    MODE   | REGISTER  |
        -----------------------------------------------------------------

        "REGISTER" indicates the number of data register.

        In the case of DIVU.L and of DIVUL.L:
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~               <ea>
        -----------------------------------------=========================
        |15 |14 |13 |12 |11 |10  | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|---|----|---|---|---|---|-----------|-----------|
        | 0 | 1 | 0 | 0 | 1 | 1  | 0 | 0 | 0 | 1 |    MODE   | REGISTER  |
        |---|-----------|---|----|---|---|---|---|-----------|-----------|
        | 0 |Dq REGISTER| 0 |SIZE| 0 | 0 | 0 | 0 | 0 | 0 | 0 |Dr REGISTER|
        ------------------------------------------------------------------

        "Dq REGISTER" indicates the number of data register for destination
        operand. This register first contains 32 bits of low weight of
        dividend, and after the value of quotient on 32 bits.

        "SIZE" specifies if dividend is on 32 or 64 bits:
        0-> 32 bits dividend placed in Dq.
        1-> 64 bits dividend placed in Dr:Dq.

        "Dr REGISTER" indicates the number of data register for destination
        operand. This register first contains 32 bits of upper weight of
        dividend if "SIZE" = 1, and after the value of rest on 32 bits.

        If Dr and Dq represents the same register, only quotient on 32 bits
        is put in Dq.

        <ea> field specifies source operand, allowed addressing modes are:

        --------------------------------- -------------------------------
        |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register|
        |-------------------------------| |-----------------------------|
        |      Dn       |000 |No reg. Dn| |   (Abs).W     |111 |  000   |
        |-------------------------------| |-----------------------------|
        |      An       | -  |    -     | |   (Abs).L     |111 |  001   |
        |-------------------------------| |-----------------------------|
        |     (An)      |010 |No reg. An| |   (d16,PC)    |111 |  010   |
        |-------------------------------| |-----------------------------|
        |     (An)+     |011 |No reg. An| |   (d8,PC,Xi)  |111 |  011   |
        |-------------------------------| |-----------------------------|
        |    -(An)      |100 |No reg. An| |   (bd,PC,Xi)  |111 |  011   |
        |-------------------------------| |-----------------------------|
        |    (d16,An)   |101 |No reg. An| |([bd,PC,Xi],od)|111 |  011   |
        |-------------------------------| |-----------------------------|
        |   (d8,An,Xi)  |110 |No reg. An| |([bd,PC],Xi,od)|111 |  011   |
        |-------------------------------| |-----------------------------|
        |   (bd,An,Xi)  |110 |No reg. An| |    #data      |111 |  100   |
        |-------------------------------| -------------------------------
        |([bd,An,Xi],od)|110 |No reg. An|
        |-------------------------------|
        |([bd,An],Xi,od)|110 |No reg. An|
        ---------------------------------

65.5. Result


        X - Not affected
        N - Set if the MSB of the quotient is 1; else cleared; undefined if
            overflow or divide by zero occurs.
        Z - Set if the quotient is zero, cleared otherwise. Undefined if
            overflow or divide by zero occurs.
        V - Set if overflow occurs, cleared otherwise. Undefined if divide by
            zero occurs.
        C - Always cleared.

        Notes:
        1. If divide by zero occurs, an exception occurs.
        2. If overflow occurs, neither operand is affected.

65.6. See also

DIVS MULS MULU