28. Bit CHanGe

28.1. Name

BCHG -- Bit change

28.2. Synopsis

        BCHG        Dn,<ea>
        BCHG        #<data>,<ea>

        Size = (Byte, Long)

28.3. Function

Tests a bit in the destination operand and sets the Z condition code appropriately, then inverts the bit in the destination. If the destination is a data register, any of the 32 bits can be specified by the modulo 32 number.

When the destination is a memory location, the operation must be a byte operation, and therefore the bit number is modulo 8.

In all cases, bit zero is the least significant bit.

The bit number for this operation may be specified in either of two ways:

  • Immediate -- The bit number is specified as immediate data.

  • Register -- The specified data register contains the bit number.

28.4. Format

        In the case of BCHG Dn,<ea>:
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~
        -----------------------------------------------------------------
        |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|-----------|---|---|---|-----------|-----------|
        | 0 | 0 | 0 | 0 |  REGISTER | 1 | 0 | 1 |    MODE   | REGISTER  |
        ----------------------------------------=========================
                                                          <ea>

        In the case of BCHG #<data>,<ea>:
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                          <ea>
        ----------------------------------------=========================
        |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|---|---|---|---|---|---|-----------|-----------|
        | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |    MODE   | REGISTER  |
        |---|---|---|---|---|---|---|---|-------------------------------|
        | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |       NUMBER OF THE BIT       |
        -----------------------------------------------------------------

REGISTER
        <ea> is always destination, addressing modes are the followings:
        --------------------------------- -------------------------------
        |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register|
        |-------------------------------| |-----------------------------|
        |      Dn *     |000 |No reg. Dn| |   (Abs).W     |111 |  000   |
        |-------------------------------| |-----------------------------|
        |      An       | -  |     -    | |   (Abs).L     |111 |  001   |
        |-------------------------------| |-----------------------------|
        |     (An)      |010 |No reg. An| |   (d16,PC)    | -  |   -    |
        |-------------------------------| |-----------------------------|
        |     (An)+     |011 |No reg. An| |   (d8,PC,Xi)  | -  |   -    |
        |-------------------------------| |-----------------------------|
        |    -(An)      |100 |No reg. An| |   (bd,PC,Xi)  | -  |   -    |
        |-------------------------------| |-----------------------------|
        |    (d16,An)   |101 |No reg. An| |([bd,PC,Xi],od)| -  |   -    | 
        |-------------------------------| |-----------------------------|
        |   (d8,An,Xi)  |110 |No reg. An| |([bd,PC],Xi,od)| -  |   -    |
        |-------------------------------| |-----------------------------|
        |   (bd,An,Xi)  |110 |No reg. An| |    #data      | -  |   -    |
        |-------------------------------| -------------------------------
        |([bd,An,Xi],od)|110 |No reg. An|
        |-------------------------------|
        |([bd,An],Xi,od)|110 |No reg. An|
        ---------------------------------
         * Long only; for others modes: Byte only.

28.5. Result

        X - not affected
        N - not affected
        Z - Set if the bit tested is zero. Cleared otherwise.
        V - not affected
        C - not affected

28.6. See also

BCLR BSET BTST EOR BFCHG