91. Signed and Unsigned MULtiply

91.1. Name

MULS -- Signed multiply
         MULU -- Unsigned multiply

91.2. Synopsis

        MULS.W        <ea>,Dn           16*16->32
        MULS.L        <ea>,Dn           32*32->32        68020+
        MULS.L        <ea>,Dh:Dl        32*32->64        68020+ (not 68060)

        MULU.W        <ea>,Dn           16*16->32
        MULU.L        <ea>,Dn           32*32->32        68020+
        MULU.L        <ea>,Dh:Dl        32*32->64        68020+  (not 68060)

        Size = (Word)
        Size = (Word, Long)                              68020+

91.3. Function

Multiply two signed (MULS) or unsigned (MULU) integers to produce either a signed or unsigned, respectivly, result.

This instruction has three forms. They are basically word, long word, and quad word. The first version is the only one available on a processore lower than a 68020. It will multiply two 16-bit integers are produce a 32-bit result. The second will multiply two 32-bit integers and produce a 32-bit result.

The third form needs some special consideration. It will multiply two 32-bit integers, specified by <ea> and Dl, the result is (sign) extended to 64-bits with the low order 32 being placed in Dl and the high order 32 being placed in Dh.

91.4. Format

        In the case of MULS.W:
        ~~~~~~~~~~~~~~~~~~~~~                              <ea>
        ----------------------------------------=========================
        |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|-----------|---|---|---|-----------|-----------|
        | 1 | 1 | 0 | 0 | REGISTER  | 1 | 1 | 1 |    MODE   | REGISTER  |
        -----------------------------------------------------------------

        In the case of MULS.L:
        ~~~~~~~~~~~~~~~~~~~~~                               <ea>
        -----------------------------------------=========================
        |15 |14 |13 |12 |11 |10  | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|---|----|---|---|---|---|-----------|-----------|
        | 0 | 1 | 0 | 0 | 1 | 1  | 0 | 0 | 0 | 0 |    MODE   | REGISTER  |
        |---|-----------|---|----|---|---|---|---|-----------|-----------|
        | 0 |Dq REGISTER| 1 |SIZE| 0 | 0 | 0 | 0 | 0 | 0 | 0 |Dr REGISTER|
        ------------------------------------------------------------------

        In the case of MULU.W:
        ~~~~~~~~~~~~~~~~~~~~~                              <ea>
        ----------------------------------------=========================
        |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|-----------|---|---|---|-----------|-----------|
        | 1 | 1 | 0 | 0 | REGISTER  | 0 | 1 | 1 |    MODE   | REGISTER  |
        -----------------------------------------------------------------

        In the case of MULU.L:
        ~~~~~~~~~~~~~~~~~~~~~                               <ea>
        -----------------------------------------=========================
        |15 |14 |13 |12 |11 |10  | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
        |---|---|---|---|---|----|---|---|---|---|-----------|-----------|
        | 0 | 1 | 0 | 0 | 1 | 1  | 0 | 0 | 0 | 0 |    MODE   | REGISTER  |
        |---|-----------|---|----|---|---|---|---|-----------|-----------|
        | 0 |Dq REGISTER| 0 |SIZE| 0 | 0 | 0 | 0 | 0 | 0 | 0 |Dr REGISTER|
        ------------------------------------------------------------------

        "REGISTER" indicates the number of data register.

        "Dq REGISTER" indicates the number of data register for destination
        operand. This register first contains 32 bits of low weight of
        dividend, and after the value of quotient on 32 bits.

        "SIZE" specifies if dividend is on 32 or 64 bits:
        0-> 32 bits dividend placed in Dq.
        1-> 64 bits dividend placed in Dr:Dq.

        "Dr REGISTER" indicates the number of data register for destination
        operand. This register first contains 32 bits of upper weight of
        dividend if "SIZE" = 1, and after the value of rest on 32 bits.

        If Dr and Dq represents the same register, only quotient on 32 bits
        is put in Dq.

        <ea> field specifies source operand, allowed addressing modes are:

        --------------------------------- -------------------------------
        |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register|
        |-------------------------------| |-----------------------------|
        |      Dn       |000 |No reg. Dn| |   (Abs).W     |111 |  000   |
        |-------------------------------| |-----------------------------|
        |      An       | -  |    -     | |   (Abs).L     |111 |  001   |
        |-------------------------------| |-----------------------------|
        |     (An)      |010 |No reg. An| |   (d16,PC)    |111 |  010   |
        |-------------------------------| |-----------------------------|
        |     (An)+     |011 |No reg. An| |   (d8,PC,Xi)  |111 |  011   |
        |-------------------------------| |-----------------------------|
        |    -(An)      |100 |No reg. An| |   (bd,PC,Xi)  |111 |  011   |
        |-------------------------------| |-----------------------------|
        |    (d16,An)   |101 |No reg. An| |([bd,PC,Xi],od)|111 |  011   |
        |-------------------------------| |-----------------------------|
        |   (d8,An,Xi)  |110 |No reg. An| |([bd,PC],Xi,od)|111 |  011   |
        |-------------------------------| |-----------------------------|
        |   (bd,An,Xi)  |110 |No reg. An| |    #data      |111 |  100   |
        |-------------------------------| -------------------------------
        |([bd,An,Xi],od)|110 |No reg. An|
        |-------------------------------|
        |([bd,An],Xi,od)|110 |No reg. An|
        ---------------------------------

91.5. Result

        X - Not affected.
        N - Set if the result is negative. Cleared otherwise.
        Z - Set if the result is zero. Cleared otherwise.
        V - Set if overflow. Cleared otherwise.
        C - Always cleared.

91.6. See also

DIVS DIVU