Invalidates selected cache lines. The data cache, both caches, or neither cache can be specified. Any dirty data in data cache lines that invalidate are lost; the CPUSH instruction must be used when dirty data may be contained in the data cache. Specific cache lines can be selected in 3 ways:
CINVL invalidates the cache line (if any) matching the physical address in the specified address register.
CINVP invalidates the cache lines (if any) matching the physical memory page in the specified address register.
CINVA invalidates all cache entries.
----------------------------------------------------------------- |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | CACHE | 0 | SCOPE | REGISTER | ----------------------------------------------------------------- CACHE: 00 - No Operation NC 01 - Data Cache DC 10 - Instruction Cache IC 11 - Both Caches BC SCOPE: 00 - Illegal 01 - Line L 10 - Page P 11 - All A