Subtracts the immediate data to the destination operand, and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size.
<ea> ----------------------------------------========================= |15 |14 |13 |12 |11 |10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |---|---|---|---|---|---|---|---|-------|-----------|-----------| | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | SIZE | MODE | REGISTER | |---------------------------------------------------------------| | 16 BITS DATA (with last Byte) | 8 BITS DATA | |---------------------------------------------------------------| | 32 BITS DATA (included last Word) | ----------------------------------------------------------------- SIZE 00->one Byte operation 01->one Word operation 10->one Long operation REGISTER <ea> is always destination, addressing modes are the followings: --------------------------------- ------------------------------- |Addressing Mode|Mode| Register | |Addressing Mode|Mode|Register| |-------------------------------| |-----------------------------| | Dn |000 |No reg. Dn| | (Abs).W |111 | 000 | |-------------------------------| |-----------------------------| | An | - | - | | (Abs).L |111 | 001 | |-------------------------------| |-----------------------------| | (An) |010 |No reg. An| | (d16,PC) | - | - | |-------------------------------| |-----------------------------| | (An)+ |011 |No reg. An| | (d8,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | -(An) |100 |No reg. An| | (bd,PC,Xi) | - | - | |-------------------------------| |-----------------------------| | (d16,An) |101 |No reg. An| |([bd,PC,Xi],od)| - | - | |-------------------------------| |-----------------------------| | (d8,An,Xi) |110 |No reg. An| |([bd,PC],Xi,od)| - | - | |-------------------------------| |-----------------------------| | (bd,An,Xi) |110 |No reg. An| | #data | - | - | |-------------------------------| ------------------------------- |([bd,An,Xi],od)|110 |No reg. An| |-------------------------------| |([bd,An],Xi,od)|110 |No reg. An| ---------------------------------
X - Set the same as the carry bit. N - Set if the result is negative. Cleared otherwise. Z - Set if the result is zero. Cleared otherwise. V - Set if an overflow is generated. Cleared otherwise. C - Set if a carry is generated. Cleared otherwise.