3. This OR That

Next up in the logical family is the OR instruction of which there are a few. OR is quite different from NOT in that it needs to have two operands in order to be used. The format of the OR instruction is :

OR.size source,Dn

or

OR.size Dn,destination

Note that in this form of the instruction either the source or the destination must be a data register. The size can be byte, word or long.

This is the 'inclusive or' instruction - there is also an 'exclusive or' variety which we will see later on in this article. An inclusive or works according to the following 'truth table' :

Table 4.1. Truth Table for Logical OR

Source bitDestination BitResulting Bit
000
011
101
111

Simply imagine each individual bit in the source is being OR'd with the same bit in the destination. The result - which will be stored in the destination bit - will always be a 1 if one OR other of the two bits being processed is a 1. If both are zero then the result will also be zero.

An example

D0.W contains $AAAA and D1.W contains $6543 the instruction

OR.W D0,D1

Will result in D1.W being set to $EFEB and D0 will remain unchanged. How does this work ? In binary :

D0 = $AAAA = 1010 1010 1010 1010
D1 = $6543 = 0110 0101 0100 0011

So using the truth table above, the result will be :

D1 = $EFEB = 1110 1111 1110 1011

The flags affected by OR are exactly the same as for NOT above.

The OR Immediate format of the OR instruction has the format :

ORI.size #data,destination

And can be byte, word or long sized. It is used when the source value in the OR is immediate data as opposed to a register or memory address. Some, but not all, assemblers will allow you to write :

OR.size #data,destination

But the actual instruction assembled will be ORI instead. Again the flags are affected as for NOT.

ORI #data,CCR 

This instruction is used to set the flags to a set of known values as supplied in the immediate data. This instruction only uses bits 0 through 4 of the data supplied as the other bits are not used in the 68008. As it is possible that future processors may introduce other flags, you are always best to make sure that bits 6 through 7 are zero when using this (and the following) instruction. That way, you won't cause any 'strange effects' on a different processor.

The flags are set as :

ORI #data,SR 

This is a similar instruction to the one above, and does a similar job except it affects the entire status register. The other difference is that the processor must be running in Supervisor mode for this instruction to be carried out. If it is not then a privilege exception will be generated - this will hang the QL (usually)

As above, the flags are set according to the data - bits 0 to 4. The rest of the status register is set as follows :

The value in bits 10, 9 and 8 can be anything from 0 through 7. This is OR'd with the current value in the interrupt level bits of the SR and the new value becomes the new interrupt level mask.

Once again, all unused bits must be zero in the data to prevent unpredictable results on different processors. (it is called defensive programming.)

This instruction can be used to turn off all interrupts except level 7. These are known as non-maskable interrupts as they cannot be turned off.

TRAP #0
ORI #$0700,SR

This sets the QL so that only a level 7 interrupt will be actioned. The only problem here is that CTRL ALT and 7 activate a level 7 interrupt and effectively hangs your QL. After the above instructions, the supervisor mode is still in effect. (Work it out in binary !!) To exit from supervisor mode ANDI #$07FF,SR would need to be done - this leads us nicely into the AND family.