In a similar manner to the OR instruction, the AND instruction needs two operands to work on to get a result.
The format of the AND instruction is :
AND.size source,Dn
or
AND.size Dn,destination
Note that as with the OR instruction, this form of the instruction requires either the source or the destination to be a data register. The size can be byte, word or long.
AND works according to the following 'truth table' :
Simply imagine each individual bit in the source is being ANDed with the same bit in the destination. The result - which will be stored in the destination bit - will always be a 1 if and only if both bits being processed are 1. If either are zero then the result will also be zero.
Using the same example as for OR above :
D0.W contains $AAAA and D1.W contains $6543 the instruction :
AND.W D0,D1
Will result in D1.W being set to $2002 and D0 will remain unchanged. How does this work ? Once again, in binary :
D0 = $AAAA = 1010 1010 1010 1010
D1 = $6543 = 0110 0101 0100 0011
So using the truth table above, the result will be :
D1 = $2002 = 0010 0000 0000 0010
The flags affected by AND are exactly the same as for NOT above.
The ANDI (immediate) instruction has the same variations as the ORI instruction as described above. These being :
ANDI.size #data,destination
And can be byte, word or long sized. It is used when the source value in the AND is immediate data as opposed to a register or memory address. Some, but not all, assemblers will allow you to write :
AND.size #data,destination
But the actual instruction assembled will be ANDI instead. Again the flags are affected as for NOT.
ANDI #data,CCR
This is an instruction that is used to reset or clear some or all of the flags. The flags are reset as follows :
C is reset if value in bit 0 of the data is a 0.
V is reset if value in bit 1 of the data is a 0.
Z is reset if value in bit 2 of the data is a 0.
N is reset if value in bit 3 of the data is a 0.
X is reset if value in bit 4 of the data is a 0.
ANDI #data,SR
This is another instruction which works on the status register but affects the entire width of the status register, not just the CCR byte.
As above, the flags are reset according to the value in bits 1 - 4 of the immediate data. The rest of the status register is reset as follows :
T (trace) is reset if the value in bit 15 of the data is 0.
S (supervisor) is rest if the value in bit 13 of the data is 0.
The value in bits 10, 9 and 8 is ANDed with the current value in the interrupt level bits of the SR and the new value becomes the new interrupt level mask.
All unused bits should be one in the data to prevent unpredictable results on different processors.
This instruction can be used to exit from supervisor mode. The instructions :
TRAP #0 ANDI #$D7FF,SR
Would set the QL so that supervisor mode was first switched on (by the TRAP #0) and then only the supervisor bit in the SR was cleared (bit 13) so the QL would revert to user mode. All other modes and interrupt levels and flags would remain unchanged.